VLSI & ES :II-MID QUESTIONS





DESIGN FOR TESTABILITY (VLSI&ES)    

SET-1

1.       Write briefly about system configuration with boundary scan using TAP controller
2.       Briefly list & explain the instructions of boundary scan test
3.       Explain about built-in logic block observer

SET-2

1.       Write a briefly note on “circular self test path system”
2.       Explain delay fault built in “self test”
3.       With neat sketch describe pin descriptions of BDSL
4.       Discuss about pin constraints of the standard for boundary scan

                                                             SET-3

1.       Explain about test per scan BIST systems
2.       Discuss about self test path system
3.       Briefly describe memory BIST
4.       Describe the economic case for BIST

                                            SET-4

1.       Define random logic BIST & explain its process
2.       Explain the pattern generation for random logic BIST
3.       Describe response compaction
4.       Discuss about BDSL description components

DSP PROCESSORS AND ARCHITECTURE  

SET-1

1.       Explain the addressing mode of TMS320 C54xx DSPs.
2.       Implement 8-point FFT on the TMS320C54xx
3.       Discuss about memory interface
4.       Write short notes on 2-D signal processing


                                                     SET-2
1.       Explain the data addressing modes of TMS320C54xx
2.       Explain the bit-reversed  index generation
3.       Write about parallel I/O interface
4.       14.Write short notes on PID controller adaptive filters
                                                        
                                                       SET-3
                      
1.       Discuss the instruction set of of TMS320C54xx
2.       Discuss interpolation  filters
3.       Explain a multichannel buffered serial port (McBSP)
4.       Discuss about memory interface

                                                         SET-4

1.       Discuss the interrupts of TMS320C54xx processor
2.       Discuss decimation filters
3.       Explain the CODEC interface with example
4.       Explain the data addressing modes of TMS320C54xx

                                                               LOW POWER VLSI

 SET-1

  1. Discuss about different types of multiplier architecture
  2. Discuss about Wallace tree multiplier
  3. Explain about low power ROM technology
  4. Briefly describe about  a)Basics of SRAM  b)Low power SRAM technologies
             SET-2
  1. Give an over view of multiplication
  2. Discuss about braun multiplier
  3. Discuss about a) Basics of ROM   b)Low power ROM
  4. Write a brief note on “memory cell”, “precharge & equalization circuit”
                               SET-3
                                                                                                          
  1. Discuss about Baugh Wooley multiplier
  2. Explain briefly about future trends & development of ROMs
  3. Discuss basics of DRAM
  4. With neat sketches explain types of multiplier architecture
                              SET-3

  1. Explain the operation of braun multiplier
  2. List out various low power-low voltage multipliers. Discuss about Wallace Tree Multiplier.
  3. Explain future trends and developments of DRAM
  4. Discuss about Low power SRAM Technologies.




















VLSI & ES :II-MID QUESTIONS VLSI & ES :II-MID QUESTIONS Reviewed by Suresh Bojja on 9/21/2015 07:00:00 AM Rating: 5

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