INDEX
S.NO | NAME OF THE E XPERIMENT | PAGE NO: | REMARKS |
1. | GATES | ||
2. | D-FLIP-FLOP-7474 | ||
3. | DECADE COUNTER-7490 | ||
4. | SHIFT REGISTERS-7495 | ||
5. | 3-8 DECODER-74138 | ||
6. | 4 BIT COMPARATOR | ||
7. | 8*1 MULTIPLEXER | ||
8. | 16*1 MULTI PLEXER | ||
9. | 4 BIT COUNTER -7493 | ||
10. | RAM (16*4) 74189(READ&WRITEOPERATIONS) |
EXPERIMENT NO-01
LOGIC GATES
AIM: Design VHDL code for all Gates:
Library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity gates is
Port ( a : in std_logic;
b : in std_logic;
c : out std_logic;
d : out std_logic;
e : out std_logic;
f : out std_logic;
g : out std_logic;
h : out std_logic;
i : out std_logic
);
end gates;
architecture Behavioral of gates is
begin
c<=a or b;
d<= a and b;
e<= a xor b;
f<= a nand b;
g<= a nor b;
h<= a xnor b;
i<= not a;
end Behavioral;
EXPERIMENT -02
D -flip- flop
AIM: Design VHDL code for D -flip- flop.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity d_ff is
Port ( d : in std_logic;
clk: in std_logic;
q : out std_logic;
qbar : out std_logic);
end d_ff;
architecture d_ff of d_ff is
begin
process(d,clk)
begin
if(clk'event and clk='1')then
q <= d;
qbar <= not d;
end if;
end process;
end d_ff;
EXPERIMENT-03
DECADE COUNTER
AIM: DESIGN VHDL CODE FOR DECADE COUNTER (7490)
library ieee;
use ieee.std_logic_1164.all;
entity mod10_counter is
port ( clk : in std_logic;
reset_n : in std_logic;
Binary : out std_logic_vector(3 downto 0));
end entity mod10_counter;
architecture mod10_counter of mod10_counter is
type state is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal Pre_state,Next_state : state;
begin
process (clk,reset_n,Next_state) is
begin
if (reset_n = '0') then
pre_state <= S0;
elsif (clk='1' and clk'event) then
pre_state <= Next_state;
end if;
end process;
process (pre_state,reset_n) is
begin
case Pre_state is
when S0 => Binary <= "0000";
if(reset_n ='1') then
Next_state <= S1;
else
Next_state <= S0;
end if;
when S1 => Binary <= "0001";
if(reset_n ='1') then
Next_state <= S2;
else
Next_state <= S0;
end if;
when S2 => Binary <= "0010";
if(reset_n ='1') then
Next_state <= S3;
else
Next_state <= S0;
end if;
when S3 => Binary <= "0011";
if(reset_n ='1') then
Next_state <= S4;
else
Next_state <= S0;
end if;
when S4 => Binary <= "0100";
if(reset_n ='1') then
Next_state <= S5;
else
Next_state <= S0;
end if;
when S5 => Binary <= "0101";
if(reset_n ='1') then
Next_state <= S6;
else
Next_state <= S0;
end if;
when S6 => Binary <= "0110";
if(reset_n ='1') then
Next_state <= S7;
else
Next_state <= S0;
end if;
when S7 => Binary <= "0111";
if(reset_n ='1') then
Next_state <= S8;
else
Next_state <= S0;
end if;
when S8=>Binary<="1000";
if(reset_n ='1') then
Next_state <= S9;
else
Next_state <= S0;
end if;
when S9=>Binary<="1001";
if(reset_n ='1') then
Next_state <= S0;
end if;
end case;
end process;
end architecture mod10_counter;
EXPERIMENT-04
DECODER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( i : in std_logic_vector(2 downto 0);
y : out std_logic_vector(7 downto 0));
end decoder;
architecture Behavioral of decoder is
with i select
Y <= "00000001" when "000" ,
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when "111",
"00000000" when others;
end Behavioral;
EXPERIMENT-05
SHIFT REGISTER
AIM: to design the VHDL code for shift register
library ieee;
use ieee.std_logic_1164.all;
entity shift_l is
port( din :in std_logic_vector(0 to 3);
clk,l,x:in std_logic;
dout :buffer std_logic_vector(0 to 3)
);
end shift_l;
architecture shift_beh of shift_l is
begin
process
begin
wait until clk'event and clk='1' ;
if (l='1')
then dout<=din;
else
genbits: for i in 0 to 2 loop
dout(i)<=dout(i+1);
end loop;
dout(3)<=x;
end if;
end process;
end shift_beh;
EXPERIMENT-06
8*1 MULTIPLEXER
AIM:DESIGN VHDL CODE FOR 8*1 MULTIPLEXER
HDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity multiplexerx is
Port ( I : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(2 downto 0);
Y : out std_logic);
end multiplexerx;
architecture Behavioral of multiplexerx is
begin
process(I,sel)is
begin
case sel is
when "000" =>Y<=I(0);
when "001" =>Y<=I(1);
when "010" =>Y<=I(2);
when "011" =>Y<=I(3);
when "100" =>Y<=I(4);
when "101" =>Y<=I(5);
when "110" =>Y<=I(6);
when "111" =>Y<=I(7);
when others =>y<='Z';
end case;
end process;
end Behavioral;
EXPERIMENT-07
16*1 MULTIPLEXER
AIM: TO Design a VHDL code for 16*1 MULTIPLEXER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity muxwith16 is
Port ( d : in std_logic_vector(15downto 0);
s : in std_logic_vector(3 downto 0);
Y : out std_logic);
end muxwith16;
architecture Behavioral of muxwith16 is
begin
process(d,s)
begin
case s is
when "0000" =>y<=d(0);
when "0001" =>y<=d(1);
when "0010" =>y<=d(2);
when "0011" =>y<=d(3);
when "0100" =>y<=d(4);
when "0101" =>y<=d(5);
when "0110" =>y<=d(6);
when "0111" =>y<=d(7);
when "1000" =>y<=d(8);
when "1001" =>y<=d(9);
when "1010" =>y<=d(10);
when "1011" =>y<=d(11);
when "1100" =>y<=d(12);
when "1101" =>y<=d(13);
when "1110" =>y<=d(14);
when "1111" =>y<=d(15);
when others =>y<='Z';
end case;
end process;
end Behavioral;
EXPERIMENT-08
4 BIT COUNTER
AIM: TO Design a VHDL code for 4 BIT COUNTER
library ieee;
use ieee.std_logic_1164.all;
entity bin_counter is
port ( clk : in std_logic;
reset : in std_logic;
Binary : out std_logic_vector(2 downto 0));
end entity bin_counter;
architecture bin_counter of bin_counter is
type state is (S0,S1,S2,S3);
signal Pre_state,Next_state : state;
begin
process (clk,reset,Next_state) is
begin
if (reset = '0') then
pre_state <= S0;
elsif (clk='1' and clk'event) then
pre_state <= Next_state;
end if;
end process;
process (pre_state,reset) is
begin
case Pre_state is
when S0 => Binary <= "000";
if(reset ='0') then
Next_state <= S0;
else
Next_state <= S1;
end if;
when S1 => Binary <= "001";
if(reset ='0') then
Next_state <= S0;
else
Next_state <= S2;
end if;
when S2 => Binary <= "010";
if(reset ='0') then
Next_state <= S0;
else
Next_state <= S3;
end if;
when S3 => Binary <= "011";
if(reset ='0') then
Next_state <= S0;
end if;
end case;
end process;
end architecture bin_counter;
EXPERIMENT-09
RAM (16*4) 74189(READ&WRITE OPERATIONS)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ramreadwrite is
port(Strobe: in std_logic; -- Enables write
Clock : in std_logic; -- System clock
reset_n : in std_logic; -- Reset
Csn : out std_logic; -- clock to the module
rdn : out std_logic; -- read enable signal
wrn : out std_logic; -- write enable signal
address out std_logic_vector(14 downto 0); -- Address Bus
data : inout std_logic_vector(7 downto 0)); -- Data Bus
end ramreadwrite;
architecture ramreadwrite of ramreadwrite is
signal count : std_logic_vector(7 downto 0)
begin
data <= count when ( Reset_n = '1' and strobe = '1') else (others => 'Z');
process(clock,strobe,reset_n)
variable add : std_logic_vector(14 downto 0);
begin
if(clock='1' and clock'event) then -- active clock edge
if(reset_n ='0') then
count <= (others => '0');
add := (others => '0');
Address <= add;
elsif (strobe = '1') then -- start writing
rdn <= '1';
wrn <= '0';
csn <= '0';
count <= count + '1'; -- data generation
add := add + '1'; --address generation
address <= add;
else -- for reading purpose
wrn <= '1';
rdn <= '0'; csn <= '0';
add := add -'1';
address <= add; end if;
end if;
end process;
end ramreadwrite;
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on
10/28/2015 03:21:00 AM
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