DSD and DICA unit wise Important Questions : M.Venkat rao , ECE Dept ,ASIST ,Paritala

Download this by clicking the below link in PDF Format


1. (a)Draw and explain design flow of HDL.
    (b)Write VHDL Code for JK flioflop using behavioural and structural modeling.
2.(a)Explain about the following (i)Packages with syntax (ii)Libraries with syntax.
          (b)Write VHDL code for D-flipflop in both structural as well as in behavioural.

3. (a)Draw and explain design flow of HDL.
   (b)Explain about the following (i)Packages with syntax (ii)Libraries with syntax.

4.(a)Write VHDL code for SR flipflpo in both behavioural and structural modeling
   (b)Compare VHDL and Verilog.


1.(a)Expain about (i)Constraints (ii)Place and route
   (b) Design representation of VHDL Modelling

2(a) Explain about following
     (i)Technology Libraries
      (ii)Static Timing

3 .(a)Explain about following 
        (i)Simulation   (ii)Synthesis
    (b)Explain the concept of internal logic synthesizer and also draw the schematic


1.Explain the internal structure of DRAM and also draw the timing diagram for read
    and write  operations.

2.(a)Explain the concept of 2D Decoding.
        (b).Draw and explain Bipolar and MOSFET SRAM cells.

3.(a)Draw and explain internal structure of ROM using 4 byte Diode Rom and
       also list advantages and disadvantages of  ROM.
  (b)Draw and explain timing diagram of SRAM(read and write operation)


      1.       (a)Design a CMOS transistor circuit for 3 input AND gate with the help of function table Explain the circuit.
(b)Explain the circuit behavior with the help  of resistive loads .with the help  of resistive loads model explain CMOS inverter.

      2.       (a)Design a CMOS OR-AND –INVERT gates(OAI) with help of functional table.
 (b)Design Basic CMOS inverter circuit with functional table

       3.       (a)Design a CMOS AND -OR–INVERT gates (AOI) with help of functional table.
        (b)Explain the following with diagrams
(i)CMOS Driving TTL in HIGH State
(ii)CMOS Driving TTL in LOW State.

4. (a)Explain the following CMOS logic families
    (i)4000 series CMOS
   (ii)HC and HCT families
   (iii)VHC and VHCT families
   (b)Design 3 input CMOS XOR,XNOR gate with help of functional table


        1. (a)Design 5*32 Decoder using one 2*4 decoder and 4 3*8 decoders ICs and explain its operation.       (b)Implement the following multiple output functions using 74LS138 and external gates.
1.       F1=Σm(1,4,5,7),         F2=ПM(2,3,6,7)

       2. (a)Design 7488157 Quad 2-i/p multiplexer and 74**153 4*1 mux with the help of logic diagram and truth tables. (b) Design 32*1 mux using two 74LS150.
       3.       (a)Design logic diagram and pin diagrams of tristate buffer ICs(74*125,74*126,74*541,74*245)
        (b)Implement the following Boolean  functions using 4:1 
                               MUX (A,B,C,D) =Σm(0,1,2,4,6,9,12,14)
4.(a)Design pin diagram and logic diagrams of IC 74*85,IC74*682(Comparators)
   (b)Draw the interfacing diagram of ten key keypad. Interface to a digital system using Decimal            to BCD  Decoder(74LS147)


1.Draw and explain the pin diagrams of 74*95 and 74*195.

2.Draw and explain pin diagrams and logic diagrams of IC74*175, IC 74*174, IC 74*374, IC 74373,74*273(MSI Registers).

3. (a)Design SSI latches and flip-flops (IC 74*74,74*1112,74*109) and explain operation of                      D,T,JK flip-flops
   (b)Convert the following
                      (i)T to D flip-flop
               (ii)JK to SR flip-flop
4.(a)Design MSI Shift register ICs and logic diagrams
  (b)Explain modes of shift registers(SISO,SIPO,PISO,PIPO)

DSD and DICA unit wise Important Questions : M.Venkat rao , ECE Dept ,ASIST ,Paritala DSD and DICA unit wise Important Questions : M.Venkat rao ,  ECE Dept ,ASIST ,Paritala Reviewed by Suresh Bojja on 11/18/2015 09:30:00 PM Rating: 5
Theme images by sebastian-julian. Powered by Blogger.