sureshQ

UNIT-III

1.       Design of halfadder, half subtractor by using basic gates  and universal gates with necessary expressions.
2.       Design fulladder& full subtractor by using universal gates and using two half sub tractors basic half adders with necessary Boolean functions.
3.       Design and 2-bit and 4-bit digital comparator.
4.       a) Implement 4:16 decoder using two 3:8 decoders.
b) Explain the operation of decoder implement 5:32 decoder using IC 74138 and 74139
5.       a) Explain operation of multiplexer and Demux with truth table with example.
b) Design 1:16 mux by using 1:4 mux and design 16:1 De-mux by using 4:1 D-mux with OR gate.
6.       a )Design Ex-3 and BCD adders with example

UNIT-IV

1.       a)Difference between PROM, PLA & PAL
b)Explain architecture of PROM, PLA, PAL
2.       BCD to Ex-3 code converter using PROM,PLA,PAL using programming tables.
3.       Implement the following function using PLA, PAL  using programming tables.
F1=∑m (0,2,4,6,8,9,15)
F2 =∑m (1, 5, 7,3,6,9,14,15)    sureshQ
4.       Design 64:4 PROM and design the PLA programming table for a combinational circuit that squares a 3-bit number.
5.       Implement the following Boolean function using PROM
F1(A1,A0)=∑m(1,2)         F2=(A1,A0)=∑m(0,1,3)
6.       Illustrate how a PLA can be used for combinational logic design with reference to functions.
F1(a, b ,c) =∑m(0,1,3,4)
=∑m(1,2,3,4,5)
Realize the same assuming that a 3x4x2 PLA is available.

UNIT-V

1.       a) Comparison between sequential circuit and combinational logic circuits.
b) Difference between synchronous and asynchronous circuits
2.       a) Design SR-latch, T-latch , D-latch  with truth tables and logic diagrams
b) Draw and explain the operation of Master Slave JK flip-flop and JK flip-flop with truth tables.
3.       Convert the following flip-flops with excitation tables
a) SR to D-flip-flop
b) D to SR-flip-flop
c) JK to D-flip-flop
d) JK to SR-flip-flop
e) D to T-flip-flops
4.       a) Design the 3-bit asynchronous counter with wave forms
b) Design the 2-bit synchronous counter with wave forms
5.       Design and explain the operations of following counters
a) Ring counter
b) Johnson counters
1.       a)Design of registers and draw and explain the various types of shift registers(SISO,SIPO,PIPO,PISO)
7. Draw and explain operation of following registers
a) Bi-directions shift registers
b) Universal shift registers           sureshQ
c) Control shift registers

UNIT-VI
1.       Explain the following related to sequential circuits with suitable examples.
a)State diagram
b)State table
c)state assignment
d)Distinguish between melay & moore machines
2.       a)Draw the Diagram of melay-type FSM for serial adder
b)Draw the  logic diagram of melay & moore model & explor its operation with examples

3.       a)Convert the following melay machine into a corresponding moore machine.

 P.S NS,X=0 Z, X=1 A B,0 E,0 B E,0 D,0 C D,1 A,0 D C,1 E,0 B,0 D,0

b)A sequential circuit has one i/p & one o/p .the state diagram is shown below. Design          sequential circuit with(a) Dff (c) RSff

4.       a)Explain about lockout condition in counter
b)Design a synchronous counter for 4  ---> 6---> 7---->3---->1 - 4 avoid lock out condition use JK type design

5.       A locked sequential circuit is provided with a single input X and sinle out put Z.whenever the input produce a string of pulses 111 & 000  ∑ at end of sequence it produces an o/p z=1 & overlapping is also required.
a)Obtain state diagram                                  sureshQ
b)Obtain state tables

6.    a)Design a melay type sequence detector to detect a serial input sequence of 101
b)Design a more type sequence detector to detect a serial input sequence of 101

STLD (Switching Theory and Logic Design ) Unit wise important questions - R13 Regulation Reviewed by Suresh Bojja on 2/06/2016 03:47:00 AM Rating: 5

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