DSD DICA I-MID Important Questions R-13 Regulation
UNIT-1
1) Explain about the Objects and Classes.
2) Write shot note on Functional Gate-Level verification
3) Write short note on package declaration.
4) Write VHDL code for D- Flip -Flop using behavioral modeling
5)Write VHDL code for half subtractor using data flow modeling.
6) Comparison of VHDL and Verilog HDL.
7) Write in brief about the history of VHDL
8) What are the steps involved in Design Flow using VHDL.
UNIT-2
1)what is logic synthesis with block diagram?
2) Explain about place and route with block diagram
3)What is simulation with block diagram
4)Explain about features of VHDL
5) Explain about following terms
(i) Technology library
(ii) Programming structure of VHDL
6) write VHDL code for half adder using structural modeling
7)Explain about inside logicsythsizer with block diagram
UNIT-3
1)Explain about following teams sureshQ
a). AND- Matrix
b). OR- Matrix
2)Implement the following function by using PLA
F1= ∑m(1,2,3) ,F2=∑m(0,1).
3) Write VHDL code for below functions using behavioral modeling
F1= ∑m(1,2,3) ,F2=∑m(0,1).
4)Explain different Commercial ROM types.
5) Explain the DRAM read and write cycle timings with help of waveforms.
7)Explain the operation of SRAM with the help of its internal architecture
8) Draw and explain the 1-bit memory cell of a Dynamic RAM
DSD DICA I-MID Important Questions R-13 Regulation
Reviewed by Suresh Bojja
on
8/10/2017 07:16:00 AM
Rating:
Reviewed by Suresh Bojja
on
8/10/2017 07:16:00 AM
Rating:
