VHDL Code for : Parity Bit Generator

library ieee;
use ieee.std_logic_1164.all;

entity par_bit_gen is
Generic(k:integer:=6);
port (din:in std_logic_vector(1 to (k+1));
par_bits:out std_logic_vector(1 to 5)
);
end entity ;

architecture v of par_bit_gen is
begin
process(din) 
variable pb:std_logic_vector(1 to 5);
begin
pb(1):=din(1) xor din(2) xor din(4) xor din(5) xor din(7);
        pb(2):=din(1) xor din(3) xor din(4) xor din(6) xor din(7);
    pb(3):=din(2) xor din(3) xor din(4);
    pb(4):=din(5) xor din(6) xor din(7);
    pb(5):=din(1) xor din(2) xor din(3) xor din(4) xor din(5) xor din(6) xor din(7)
           xor pb(1) xor pb(2) xor pb(3) xor pb(4);
    par_bits<=pb;
end process;
end architecture ;
VHDL Code for : Parity Bit Generator VHDL Code for : Parity Bit Generator Reviewed by Suresh Bojja on 9/07/2018 09:33:00 PM Rating: 5

Subjects & Labs

Theme images by sebastian-julian. Powered by Blogger.